AN4065 - QDR®-II, QDR-II+, DDR-II, and DDR-II+ Design Guide | Cypress Semiconductor
AN4065 - QDR®-II, QDR-II+, DDR-II, and DDR-II+ Design Guide
Cypress Quad Data Rate™ (QDR®)-II, QDR-II+, DDR-II, and DDR-II+ SRAMs address the high-bandwidth requirements for networking and data storage applications that provide up to 80 GBps data transfer rate. The purpose of this application note is to assist system designers in using the QDR-II, QDR-II+, DDR-II, and DDR-II+ SRAM devices. It includes guidelines on clocking and termination techniques for the QDR-II, QDR-II+, DDR-II, and DDR-II+ SRAM devices.
(Clocking Strategy for QDR-II+ using Echo Clocks CQ and CQ#)
Dear valued customer,
Thank you for choosing our products. They come with all the know-how and passion that our engineers have put into it. As you probably already know, Cypress is now Infineon. This is a major step for our company, but also for the good of you.
Reliability and business continuity are of utmost importance for us. Hence, we remain fully committed to honoring existing customer and distributor relationships. This includes offering the legacy Cypress product portfolio. We thank you very much for your trusting support.
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|File Title||Language||Size||Last Updated|
|AN4065 QDR-II, QDR-II+, DDR-II, and DDR-II+ Design Guide.pdf||English||1.18 MB||08/26/2015|
|AN4065 QDR®-II, QDR-II+, DDR-II, and DDR-II+ Design Guide (Chinsese).pdf||Chinese||1.3 MB||08/01/2017|
|AN4065 QDR-II, QDR-II+, DDR-II, and DDR-II+ Design Guide (Japanese).pdf||Japanese||1.26 MB||08/26/2015|
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