You are here

Descriptor System Data Transfer (PDL_DSTC) | Cypress Semiconductor

Descriptor System Data Transfer (PDL_DSTC)

Last Updated: 
Nov 06, 2016
  • Data transfer across a CPU-independent bus
  • Up to 64 transfer channels in the FM0+ family devices
  • Transfers triggered from Software or Hardware
  • Supports a 32-bit address space
  • Supports chained transfers with flexible reload functions
Symbol Diagram


General Description

The Descriptor System Data Transfer Controller Component can transfer data at high speed, bypassing the CPU, to any memory-mapped location in the device. The Descriptor (DES) System Model is extremely flexible and enables engineers to create sophisticated memory transfer schemes. Transfers can be triggered from either hardware or software and can be chained using inner and outer (with respect to the block of memory) reload functions. Interrupts indicate success or failure and parity checksum ensures DES integrity prior to a transfer.

DSTC Component Parameter Editor