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EZI2C Slave | Cypress Semiconductor

EZI2C Slave

Last Updated: 
Mar 19, 2018
  • Industry standard NXP® I2C bus interface
  • Emulates common I2C EEPROM interface
  • Only two pins (SDA and SCL) required to interface to I2C bus
  • Standard data rates of 50/100/400/1000 kbps
  • High level APIs require minimal user programming
  • Supports one or two address decoding with independent memory buffers
  • Memory buffers provide configurable Read/Write and Read Only regions
Symbol Diagram
EZI Ziagram

General Description

The EZI2C Slave component implements an I2C register-based slave device. It is compatible with I2C Standard-mode, Fast-mode, and Fast-mode Plus devices as defined in the NXP I2C-bus specification. The master initiates all communication on the I2C bus and supplies the clock for all slave devices. The EZI2C Slave supports standard data rates up to 1000 kbps and is compatible with multiple devices on the same bus.

The EZI2C Slave is a unique implementation of an I2C slave in that all communication between the master and slave is handled in the ISR (Interrupt Service Routine) and requires no interaction with the main program flow. The interface appears as shared memory between the master and slave. Once the EZI2C_Start() function is executed, there is little need to interact with the API.

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