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Filter | Cypress Semiconductor


Last Updated: 
Nov 20, 2018

  • Easy filter configuration using the Digital Filter Block (DFB) available in select PSoC 3 and PSoC 5 LP devices
  • Supports two separate filter channels, each one constructed as a cascade of up to four separately designed stages.
  • Multiple FIR and IIR (Biquad) filter methods
  • Support for flexible coefficient entry
  • Final coefficient values available for further analysis
Symbol Diagram

Filter 1 Image

General Description

The Filter component allows easy creation of single or dual channel digital filters using the DFB. The component includes a filter design feature, which greatly simplifies the design and implementation processes. It supports two streaming channels that can be streamed directly from other hardware blocks (such as the ADC) using DMA. The filtered results can likewise be transferred using DMA, interrupts, or polling methods. The DFB’s 128 data and coefficient locations are shared as needed between the two filter channels, and this information is used to guide the choice of filter implementation. It reports (but does not set) the minimum bus clock frequency required to execute the filtering within the declared sample interval. This clock can then be set in the design-wide resource manager.

The Filter component supports many use cases. If something unusual occurs when using it, please report it (with a good description). Either email or contact tech support at

PSoC® Creator Filter 2.0 Component Video


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